Generally, metal wirings of semiconductor devices are formed by using metal thin films made of metals such as Al or Cu etc., and electrical connections and pad connections between the semiconductor devices allow circuits formed in a semiconductor substrate to be connected to each other.
Such metal wiring for connecting device electrodes and pads separated by an insulating film such as an oxide film or the like are formed through dual damascene process including a step of selectively etching the insulating film to form a via hole, filling an inside of the via hole with a filling film by using a photosensitive film, forming a trench pattern on the insulating film by using the photosensitive film, etching the insulating film to form a trench by using the trench pattern as a mask, removing the trench pattern and the filling film, and filling the inside of the via hole and the inside of the trench with the metal film.
A plurality of metal wirings formed through the dual damascene process described above may be formed with a multiple-layered structure. In such a case, there may exist parasitic capacitances between upper and lower overlapping and parasitic capacitances between neighboring metal wirings, thereby decreasing the operational speed of the semiconductor device.
Accordingly, in order to reduce the parasitic capacitances, the insulating film for surrounding and supporting the metal wirings is conventionally made of a lower dielectric (low-k) material.
Meanwhile, the via holes are filled with a film having an etching selectivity lower than that of the insulating film. That is, if the insulating film and the photosensitive film are simultaneously etched for an arbitrary predetermined time period, the amount of the photosensitive film etched away is smaller than that of the insulating film. As a result, fences are formed on a lower surface of the trench due to the difference in the etching selectivity between the insulating film and the photosensitive film. The height of the fences made as described above may be lowered by a following process such as a process for removing the photosensitive film positioned within the via hole, but the fences may not be completely removed.
Accordingly, when the trench and the via hole are filled with a metal thin film, a height difference generated by the fences causes the trench and the via hole to be incompletely filled with the metal thin film, and a crack may develop at the metal wirings. This may increase the resistance of the metal wirings, adversely affecting the characteristics of the semiconductor device, degrading its reliability.
Also, residues generated by performing the etching process of the low-k material using the dual damascene process two times are left on the inside walls of the via hole and the trench. The residues increase the resistance of the semiconductor device, decreasing the operational speed of the semiconductor device.
In addition, when the low-K material is patterned through the dual damascene process, the low-K material exposed by performing the asher process and an asher liquid are chemically reacted to increase the dielectric constant (K) of the low-K material. As a result, the operational speed of the semiconductor device may be lowered.